1. Field of the Invention
The present invention relates generally to moving average processors and, more particularly, to a configuration of a processor capable of obtaining a moving average at high speed with a simple circuit configuration.
2. Description of the Background Art
Various kinds of sensors are generally used for monitoring the state of an object to be measured. It is necessary to remove noise components included in outputs of the sensors in order to precisely determine the state of the object to be measured. In order to remove noises included in a signal sequence such as the sensor outputs or like and to provide an accurate input signals sequence, the input signal sequence is often subject to moving average processing.
The moving average is a method of taking the average value of several terms adjacent to data Ai in the case that a series of data (a series of sampled values sampled in a predetermined sampling period) {Ai} is supplied. In the case that a series of input data is a series of sampled values which are made discrete in time, the moving average processing corresponds to low-pass filter processing. There are two main conventional methods of performing the moving average processing. The one is software processing and the other is hardware processing with a digital filter. These methods will now be described.
First of all, a description will be given on the method of obtaining the moving average by the software processing. In this method, the series of input data is first stored in a storage in a processing system such as a computer. In the case of the moving average processing of five terms, for example, the following arithmetic operation is sequentially preformed. EQU A.sub.i =(A.sub.i-2 +A.sub.i-1 +A.sub.i +A.sub.i+1 +A.sub.i+2)/5(1)
In this case, respective data stored in the storage of the processing system are sequentially read out, so that the arithmetic operation of the above expression (1) is performed for the respective read-out data. This operation is not performed actually by one-time arithmetic operation but by several times of adding operation and one-time of dividing operation.
In the hardware processing, the above expression (1) is processed by hardware. FIG. 1 shows an example of the configuration of a device for performing the moving average processing on five terms, employing a digital filter (an FIR filter: a finite impulse response filter).
Referring to FIG. 1, a conventional moving average processor comprises cascade-connected first through fourth delay elements 51a, 51b, 51c and 51d, multipliers 52a, 52b, 52c, 52d and 52e for multiplying input data and the respective outputs of the delay elements 51a to 51d by their respective predetermined coefficients, and cascade-connected first through fourth adders 53a, 53b, 53c and 53d for adding the respective outputs of the multipliers 52a to 52e to output the result of the addition.
The first through fourth delay elements 51a-51d delay supplied data by the time corresponding to one sampling period of the input data and then transmit the delayed data to the delay elements at their succeeding stages, respectively. The multiplier 52a multiplies the input data supplied from an input terminal 54 by a coefficient (1/5) to output the result of the multiplication. The multiplier 51b multiplies the output of the first delay element 51a by the coefficient (1/5) to output the result of the multiplication. The multiplier 52c multiplies the output of the second delay element 51b by the coefficient (1/5) to output the result of the multiplication. The multiplier 52d multiplies the output of the third delay element 51c by the coefficient (1/5) to output the result of the multiplication. The multiplier 52e multiplies the output of the fourth delay element 51d by the coefficient (1/5) to output the result of the multiplication.
The first adder 53a adds the output of the multiplier 52a and that of the multiplier 52b. The second adder 53b adds the output of the multiplier 52c and that of the adder 53a. The adder 53c adds the output of the multiplier 52d and that of the adder 53b. The fourth adder 53d adds the output of the fifth multiplier 52e and that of the third adder 53c. Output data is outputted via an output terminal 55 from the adder 53d. An operation will be described briefly.
A case is now considered that the sampling data A.sub.i is supplied to the input terminal 54. At this time, the delay elements 51a-51d output input data A.sub.i-1 preceding by one sampling period to the present data, input data A.sub.i-2 preceding by two sampling periods, input data A.sub.i-3 preceding by three sampling periods, and input data A.sub.i-4 preceding by four sampling periods, respectively. The multipliers 52a-52e multiply the respective supplied data by the respective coefficients (1/5) to output the results of the multiplication to the associated adders. Therefore, the fourth adder 53d outputs data expressed below: EQU (A.sub.i +A.sub.i-1 +A.sub.i-2 +A.sub.i-3 +A.sub.i-4)/5 (2)
and, the data of the above expression (2) is outputted as output data (a moving average value) from the output terminal 55.
Although the expression (2) seems different from the previous expression (1), a series of data to be outputted is a series of moving average values of the input data sequence supplied to the input terminal 54, which is expressed as ##EQU1## thus providing the same arithmetic operation.
In the case of performing the moving average processing by employing the described software processing, many times of adding operations are necessary for one-time data processing, and thus it is generally difficult to carry out the moving average processing at high speed. That is, in order to perform the operation of the above expression (1) or (2), the following step is usually carried out, for example: first of all, one data is added to the other, and the result of this addition is stored in a register. A value stored in this register is then added to the succeeding data. A dividing operation is carried out after this adding operation is carried out predetermined times (four times in the above described expression). The dividing operation in the software processing is usually the same as a subtracting operation, i.e., the adding operation. Thus, this dividing operation requires plural times of the adding operations in data processing by the software processing, and hence fast moving average processing cannot be carried out. Furthermore, in order to perform the operation of the above expression (1) or (2), a storage such as a register becomes necessary for storing input data and output data.
Meanwhile, in the method of carrying out the moving average processing by hardware employing a digital filter, this arithmetic operation can generally be carried out at higher speed than in software processing. However, for performance of the moving average processing of M terms, M multipliers and (M-1) adders are required, resulting in enlargement of the device. Further, once hardware implementation is fixed, processing conditions such as the number of terms of the moving average is uniquely determined, and thus it is difficult in general to alter these conditions.
Examples of the "digital filter" in software and hardware implementations are respectively shown in Journal "Interface", published by CQ Shuppan, November 1987, pp. 268-269.
A hardware implemented moving average processor is disclosed in Japanese Patent Laying-Open Nos. 63-187366 and 63-19071.